Memory arrays typically are formed of a multiplicity of symmetrical memory cells organized into columns. Each cell is formed of at least one transistor and has a gate, a source at one side and a drain on the other side. Rows of gates are connected together into word lines and columns of sources and of drains are connected together into bit lines.
In virtual ground memory arrays, where the transistors are symmetrical, the bit lines can act either as source lines or as drain lines, depending on the voltage placed on them. In non-virtual ground memory arrays, the bit lines formed of columns of sources are dedicated as source lines and the bit lines formed of columns of drains are dedicated as drain lines or "read" lines.
When reading a selected memory cell, the bit line which is the drain is precharged to a predetermined level and the memory cell is read by removing charge from the drain line. It will be appreciated by those skilled in the art that the reading time is inversely dependent on the capacitance of the drain line and that the capacitance of each drain line is a function of the accumulation of the capacitance of the many memory cells attached to it.
In order to pre-charge the bit lines, they are connected to a capacitive node, known herein as the common node bit line (CNBL), to which a pull-up transistor is connected. This is illustrated in FIG. 1 to which reference is now made.
The pre-charge system of FIG. 1 includes a CNBL line to which a multiplicity of bit lines, divided into source lines 10 and drain lines 12, are attached via equalization (EQ) transistors 14. The CNBL line is connected to a pull-up transistor 16 which attempts to pull the voltage of the bit lines up to a voltage defined by a voltage reference source Vref. The other end of the bit lines 10 and 12 are connected to a decoder 18 which determines which of the bit lines 10 and 12 are to be used to read data stored in a selected memory cell.
Once a read cycle starts, indicating that a memory cell will shortly be read, all of the EQ transistors 14 are activated in order to connect all of the bit lines 10 and 12 to the CNBL line, thereby causing, through the activity of the pull-up transistor 16, the bit lines 10 and 12 to be pre-charged to a desired voltage level. At the end of a first interval, the EQ transistors 14 connected to the source lines 10 are deactivated, thereby disconnecting the source lines 10 from the CNBL line. The EQ transistors 14 connected to the read lines 12 remain activated until the end of the pre-charge interval.
During the pre-charge interval, the decoder 18 determines which source line 10 and which read line 12 are to be utilized for reading the selected memory cell. Once the first interval is over, the selected source line 10 begins to be discharged while the read lines continue to be pre-charged. At the end of the pre-charge interval, the memory cell (not shown but between the selected source and read lines 10 and 12) can be read.
It is noted that, in the prior art pre-charge system shown in FIG. 1, the selected source line 10 is first pre-charged, only to be discharged immediately thereafter. The time allotted for pre-charging is typically the maximum time it takes for the memory array to become pre-charged. The time allotted for discharging the selected source line 10 is also the maximum time necessary. Therefore, the pre-charging causes a delay between the start of a read cycle and the time when reading actually occurs.
Furthermore, in the prior art, the read and source lines are selected only once the voltage on a word line WL, connecting a row of memory cells, has "ramped up" to its full value. This is a time-consuming process, especially if the pre-charging process takes a significant amount of time.